FPGA Implementation of High-Dependability RISC-V Processor System 1 set

⑴ Classification of the products to be procured : 71 ⑵ Nature and quantity of the products to be purchased : FPGA Implementation of High-Dependability RISC-V Processor System 1 set ⑶ Delivery period : From 4 September, 2026 through 31 March, 2027 ⑷ Fulfillment place : Institute of Science Tokyo Ookayama area ⑸ Qualifications for participating in the tendering procedures : Suppliers eligible for participating in the proposed tender are those who shall : A not come under Article 7 and 8 of the Regulation concerning the Contract for Institute of Science Tokyo, B have the Grade A, Grade B or Grade C qualification during fiscal 2026 in the Kanto・Koshinetsu area in offer of services for participating in tenders by Single qualification for every ministry and agency, However, entities rated as Grade D are also eligible, provided they meet the technical requirements. C meet the qualification requirements which Institute of Science Tokyo may specify in accordance with Article 6 of the Regulation, D not be currently under a suspension of business order as instructed by Institute of Science Tokyo. ⑹ Time limit of tender : 17 : 00 17 August, 2026 ⑺ Contact point for the notice : Norimitsu Suwa, Procurement Division, Finance Department, Institute of Science Tokyo, 2-12-1 Ookayama, Meguro-ku, Tokyo 152-8550 Japan, TEL 03-5734-2355 e-mail : proc.oka4@adm.isct.ac.jp ⑻ Please be noted that if it is indicated that environmental conditions relating to the procurement are laid down in its tender documents. 0071 Computer & Related Services